Courses and talks
(Last modified Apr 18, 2005)
 
 
Short course 1
 
Title: Gigabit Networking for Data Acquisition Systems - A practical introduction
 
Speaker: Artur Barczyk, CERN
 
Time: Sunday June 5. Preliminarily 9.30 - 13.00 with breaks
 
Abstract:
 
    Modern DAQ systems deploy ever more COTS (Commercial Off The Shelf) equipment for delivery of data to the processing units. This short course offers a practical introduction to the design of data acquisition systems based on gigabit network technology.

    Based mostly on experience with Gigabit Ethernet, the course covers, from a practical point of view, the basics of LAN design and operation, switch technologies, network protocols, Linux networking basics, and presents the methods and tools used in design as well as performance evaluation and prediction. We will present how some more advanced concepts such as Virtual LANs, Quality of Service and Multicasting can be usefully deployed in DAQ systems of any scale.

    The course is meant mainly for DAQ scientists not (yet) familiar with networking, potentially interested in the implementation and/or use of gigabit networks in their systems.

    The topics covered are:

    • Network architecture
    • Protocol Layers
    • Switch architectures
    • Real-world switch properties
    • Quality of Service features
    • VLANs
    • Multicast traffic
    • Linux network basics and software tools
 
Short course 2
 
 
Title: System On Programmable Chip - A design tutorial
 
Speaker: Simon George, Xilinx
 
Time: Sunday June 5. Preliminarily 14.00 - 17.30 with breaks
 
Abstract:
 
    FPGAs have reached such a high complexity and capacity to make Systems On Programmable Chip a reality today. Both hard and soft FPGA Embedded processors enable designers to create complete solutions for Embedded systems, quickly, easily and flexibly without compromising performance and functionalities.

    Learn why FPGA embedded processors are changing the designer approach to embedded design, what is available to the designer today, what tools will help to achieve desired goals. In this overview Xilinx will show the broad range of processors available and which system designs will be a perfect target for the FPGA architecture.

    You will learn how to design your HW, your SW application and combine them together with or without a complex Real Time Operating System. You will learn how HW and SW partitioning is made flexible and simple. How you can accelerate critical SW loops in HW and combine General Purpose Processing with DSP functions in the same chip.

    What about connectivity? Very often there is a need to fast transfer data in and out of your System On Chip. Ethernet, USB, HDLC and other available options will be reviewed. Multi Gigabit Transceiver technology for High Speed communication and Gigabit System reference design techniques will be discussed to exploit TCP/IP over Ethernet at wire-line speed.

    Moreover, HW and SW combined debugging is crucial for getting a perfectly functional design in a very short time. See how Xilinx addresses this challenge with the EDK SW debugger combined with Chipscope Pro to simultaneously debug HW and SW platforms.

    Finally a quick look into the future will show trends and technology for the years to come.

 
 
Introductory talk 1
 
Title: Solar Adaptive Optics Using Off the Shelf Computing Hardware
 
Speaker: Göran Scharmer, Peter Dettori
 
Time: Monday 6/6, 10:00 - 10:30
 
Abstract:
 
    The 1-meter Swedish solar telescope (SST) is a new solar telescope that was put in operation on the island of La Palma in the Canary Islands at the end of May 2002. The goal of this telescope was to reach its diffraction limited resolution of 0.1 arcsec in blue light. This has already been achieved by use of a low-order adaptive optics (AO) system. Solar Adaptive Optics (AO) is computationally more demanding than night-time AO because on the sun, there are no point sources on which to lock. Solar AO needs cross-correlation algorithms to measure image motion needed for the wavefront sensor controlling the AO. To date efforts to build solar AO instruments can been divided into 2 groups, those that use FPGAs and those that use general purpose processors. We at the SST have for a long time been advocating the later.

    The SST is operated by a very small institute and for this reason has for a long time developed all instrumentation based on standard hardware. The current system runs on a dual Xeon computer running Linux with Real Time Application Interface. While resources have been a primary factor in the decision to development on off the shelf hardware we do not feel hindered by this, but see several advantages in our strategy such as a much shorter development time and the benefit of being able to easily upgrade to faster processors on a regular basis.

    This paper briefly describes how a Solar AO system works. We will detail the development of AO at the the former 50-cm Swedish Vacuum Solar Telescope (SVST) through to current and planned SST systems. We will describe in detail the real time constraints on the system and detail the current performance that we obtain. To get the most out of standard processors is is essential that one carefully optimises critical paths of the code. Rewritting selected, small regions of 'C' code in assembler code has yielded huge improvements without which our systems would never have worked. We will go through these changes in detail and present some of the results we have achieved.

 
 
Introductory talk 2
 
Title: A Review of Techniques and Technologies for the Transport of Digital Data in Recent Physics Experiments
 
Speaker: D. Calvet, CEA Saclay, Gif sur Yvette, FRANCE
 
Time: Tuesday 7/6, 9:00 - 9:30
 
Abstract:
 
    This paper presents past and present techniques and technologies for the transport of digital data in physics experiments. After a description of the typical requirements of modern data acquisition systems in the field of large scale experimental physics, we detail the successes and failures observed over the last 20 years of evolution of high-speed point-to-point link technology, networking standards and products. Modern data transport technology is presented along with several applications to experiments under construction. Advanced techniques, emerging technologies and trends in the field of high-speed digital data transport are outlined in the perspective of future experiments.
 
 
Introductory talk 3
 
Title: Data Processing for In-Beam Positron Emission Tomography
 
Speaker: Wolfgang Enghardt, Forschungszentrum Rossendorf, Institute of Nuclear and Hadron Physics, Dresden, Germany
 
Time: Wednesday 8/6, 9:00 - 9:30
 
Abstract:
 
    In-beam positron emission tomography (PET) is currently the only method for an in-situ monitoring of highly tumour-conformed charged hadron radiotherapy. In-beam PET is based on the positron emitters that are produced as a by-product of tumour irradiation via the interaction of the particle beam with the atomic nuclei of the tissue. Therefore, a PET scanner has to be physically and logically integrated into a radiotherapeutical treatment unit for imaging simultaneously with the tumour irradiation this low level radioactivity distribution, which has to be discriminated against an enormous background burden to the PET detectors caused by nuclear reactions induced by the therapy beam. Furthermore, to deduce the desired clinical information, the measured activity distributions have to be compared with those, predicted from the treatment plan as well as from the time course of the tumour irradiation. These particularities of in-beam PET require dedicated technical solutions in data acquisition and processing, which are beyond the standard technology known from PET for tracer imaging in nuclear medicine. Their implementation is explained for the in-beam PET scanner installed at the experimental carbon ion tumour therapy facility at the Gesellschaft für Schwerionenforschung Darmstadt, Germany. The clinical feasibility of the in-beam PET technology has been demonstrated by monitoring the fractionated radiotherapy of more than 250 patients over the last seven years.
 
 
Introductory talk 4
 
Title: Instrumentation Standard Architectures for Future High Availability Control Systems
 
Speaker: R. S. Larsen, Stanford Linear Accelerator Center, Menlo Park California USA
 
Time: Friday 10/6, 9:00 - 9:30
 
Abstract:
 
    This paper proposes design goals for next-generation modular instrumentation standards, in particular stressing basic architectures that will meet a system requirement of High Availability, or robustness against system failure. New standards should be based on architectures that (1) are modular in both hardware and software for ease in repair and upgrade; (2) include inherent redundancy at internal module, module assembly and system levels; (3) include modern high speed serial inter-module communications with robust noise-immune protocols; and (4) include highly intelligent diagnostics and board-management subsystems that can predict impending failure and invoke evasive strategies. The simple design principles lead to fail-soft systems that can be applied to any type of electronics system, from modular instruments to large power supplies to pulsed power modulators to entire accelerator systems. The existing standards in use are briefly reviewed and compared against a new commercial standard which suggests a powerful model for future laboratory standard developments. The past successes of undertaking such projects through inter-laboratory engineering-physics collaborations will be briefly summarized.

    Work supported by US DOE Contract DE-AC03-76SF00515